1. Field of the Invention
The present invention relates to devices for data storage and retrieval. Particularly, this invention relates to a magnetoresistive random access memory device (MRAM), which may be implemented using a resistive cross point memory (RXPtM) cell array (although the invention is not so limited), and to method and apparatus for automatically determining an optimized level (or levels) of writing current to record a binary data bit in a memory cell of such an array. Moreover, a memory device embodying the invention may also be of a type other than resistive cross point MRAM memory, such as of an MRAM memory with series diode or transistor switch elements.
The current which is used to record a binary data bit (i.e., a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) in a memory cell of a memory device embodying the invention is termed a xe2x80x9cwrite current,xe2x80x9d or xe2x80x9cwriting current,xe2x80x9d and this invention provides a method and apparatus for optimizing such writing current. Further, this invention relates to such a method and apparatus in which the memory cell array, and a write controller most preferably are both defined on the same chip (i.e., on the same substrate). More particularly, this invention relates to a method and apparatus for determining a write current level which is optimized not only with respect to writing data into a selected memory cell in which it is desired to record a binary data bit, but also with respect to maintaining data integrity in other non-selected memory cells in which other data may be written, and which other data is not to be compromised even though the non-selected memory cells are exposed to a magnetic effect from the writing current.
2. Related Technology
Magnetoresistive Random Access Memory (xe2x80x9cMRAMxe2x80x9d) is a non-volatile memory that is being considered for long term data storage. A typical MRAM device includes an array of memory cells. In one embodiment of MRAM, word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Thus, the memory cells are each located at a cross point of a word line and a bit line, and each memory cell includes two masses of magnetic material. One of the masses is magnetically fixed and the other is magnetically variable. A memory cell stores a bit of information as the relative orientation of the magnetizations of the fixed and variable magnetic materials. In other words, the magnetization of each memory cell at any given time assumes one of two stable orientations. These two stable orientations, referred to as xe2x80x9cparallelxe2x80x9d and xe2x80x9canti-parallelxe2x80x9d magnetic orientation, represent logic values of xe2x80x9c0xe2x80x9d and xe2x80x9c1,xe2x80x9d for example. The resistance of a memory cell varies dependent upon whether it stores a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d value. That is, the resistance of a memory cell is a first value xe2x80x9cRxe2x80x9d if the orientation of the magnetizations of the fixed magnetic material and of the variable magnetic material is parallel, and the resistance of the memory cell is increased to a second value R+AR if the orientation of the magnetizations is anti-parallel. The relative orientation of the magnetizations of a selected memory cell (and, therefore, the logic state of the memory cell) may be read by sensing the resistance value of the selected memory cell. Thus, this embodiment of an MRAM memory device can be referred to as a Resistive Cross Point Memory (RXPtM) Cell Array, and this name has reference to the fact that the memory cells change in apparent resistance value dependent upon whether they store a binary one, or a binary zero.
Performing read and write operations in MRAM devices could be orders of magnitude faster than performing read and write operations in conventional long term storage devices, such as hard drives, for example. In addition, the MRAM devices could be more compact and could consume less power than hard drives and other such conventional long term data storage devices.
However, writing data into MRAM cells requires that a writing current be applied to both the word line and to the bit line that cross at a selected memory cell. Thus, it is clear that one of the particular word line and bit line crosses other non-selected memory cells in which other data may already be stored. The write current used to effect writing of data into the selected memory cell must be high enough to reliably effect the orientation of the magnetic field in that selected memory cell (referred to as a xe2x80x9cwrite current thresholdxe2x80x9d), but not so high as to effect the magnet field orientation at any non-selected memory cell (referred to as the xe2x80x9chalf select thresholdxe2x80x9d). The non-selected memory cells are referred to also as half-selected memory cells because these memory cells are exposed to only one of the word and bit lines to which the write currents are applied, and thus are exposed to about one-half of the write current.
Further, it appears that the write current necessary to write a data bit into MRAM cells differs dependent upon whether the data bit to be written is a binary xe2x80x9c1xe2x80x9d or a binary xe2x80x9c0.xe2x80x9d In other words, the direction of orientation of the magnetic field in the variable layer of magnetic material may be more difficult to change from a first orientation to the second orientation than it is to change from the second orientation to the first orientation. This phenomenon has an influence upon the write threshold and the half select threshold, because a bit line write current optimized to reliably write a data xe2x80x9c1xe2x80x9d may not be optimum to write a data xe2x80x9c0.xe2x80x9d Thus, these memory cells which are ready to change magnetic field orientation in the easy direction are particularly susceptible to a loss of the stored data values.
While it appears that the write current threshold and half select threshold of MRAM cell arrays are substantially constant throughout the life of each array, the current levels for each particular array appears to be dependent upon a number of design variables, fabrication variables, geometry variables, and process variables. Thus, each particular MRAM cell array needs to have its write current and half select currents determined. Further, these current values may change in view of some environmental factors for each particular MRAM cell array, such as changes in operating temperature and/or changes in the operating voltage of the memory cell array.
Thus, there is a need to reliably write data to memory cells in an array of MRAM cells (i.e., in RXPtM devices, for example) while safely preserving the integrity of data in other cells of the array of memory cells.
Currently, it is known to calibrate write current power supplies for MRAM cell arrays using a laboratory procedure. That is, a test engineer works with a particular array of memory cells over a period of time to determine the appropriate level of write current to apply to the word and bit lines. This laboratory procedure is not appropriate or practicable for serial production of MRAM cell arrays at a commercially viable cost.
Thus, there is a need to provide a method which may be automated so as to determine optimum writing current levels for a MRAM cell array.
These needs are met by the present invention. According to one aspect of the present invention, a first pair of write current power supplies (i.e., a xe2x80x9crowxe2x80x9d power supply and a xe2x80x9ccolumnxe2x80x9d power supply) are calibrated for a particular MRAM cell array by successively applying an incrementally increased write current to selected memory cells of the array, and then testing for the integrity of the written data after every application of the write current. When no writing errors are detected, it is noted that a current level has been reached that will reliably write data to the particular memory cell array. Thus, it is known that current levels at or above this threshold current level will reliably write data to the particular memory cell array.
However, the question remains as to how high the write current may be without also being above the half select threshold. Thus, to determine the half select threshold for the particular memory cell array, one of the power supplies is used to apply only one of the write currents (i.e., a half current) to only one of the word or bit lines, and this half current is again incrementally increased, and the data stored in particular memory cells crossed by the word or bit lines is tested for data invalidities after each incremental increase of the writing half current. When a half current level is reached at which data invalidities begin to occur, the half current level is noted. A preferred write current level is an average of the current level for reliable writing and the current level at which data invalidities result from the half select current level
Further, a method of determining the appropriate write current level for an array of similar MRAM memory cells includes utilization of a particular algorithm for selecting the write current for rows of the memory cells, for columns of the memory cells when writing a digital one, and for columns of the memory cells when writing a digital zero.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.